ContributorHi David,
Apologize for the late response as I had been busy on other stuff.
May I know if there is any update/progress you can share on the platform system simulation and the example design
Super ContributorSun,
May I know if you are able to simulate the IP?
Any update on the script etc?
ContributorHi SyafieqS,
Thank you for asking. I couldn't simulate the IP. I have a project to implement ultrasound system based on Arria 10 development kits.
the initial design is from TI demo project. first I plan to create a system simulation platform. I have an I2C module as command input interface. now it is working. So I can visit the FPGA register through the I2C master module. the Nios2 is working in the simulation platform too, I can set the FPGA IO through the Nios2 program. I still have few function blocks to overcome.
1 is the DDR, functional module. 1 is the Jesd interface module. 1 is PCIe or USB3, FX3 interface.
now I am struggling with the intel AN812, I downloaded Qsys_pro_tutorial_design_arria_10_17p0. I loaded on the dev board and it working.
I have been working for several days to create an simulation, but still not successful. for some reason, I couldn't see any toggling on the CPU data and instruction bus. I can see the nios2 ram with program like contents. and both reset and clock are OK. for a generic cpu, it should start read and write the memory after release the reset. don't know why this one doesn't.
once I can run DDR interface, I will go back to AN803. if you can provide me some suggestion on AN803, I can work on it first, and visit AN812 later. it is a long way to go, but I already far from the start point.
Intel tools and everything are so powerful, so it is reasonable for a painful learning curve.
Thank you vey much,
David
