Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

ALTPF_divide tool from Quartus

hi,

i am trying to use the MegaWizard tool for floating point division from Quartus, but when i run the test bench for the design i keep getting this error message

Fatal error in Process MEMORY at C:/altera/12.0/modelsim_ase/win32aloem/../altera/vhdl/src/altera_mf/altera_mf.vhd line 39809

# HDL call sequence:

# Stopped at C:/altera/12.0/modelsim_ase/win32aloem/../altera/vhdl/src/altera_mf/altera_mf.vhd 39809 Subprogram read_my_memory

# called from C:/altera/12.0/modelsim_ase/win32aloem/../altera/vhdl/src/altera_mf/altera_mf.vhd 41612 Process MEMORY

can anyone help me with this please?

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    and here is the test bench i am using

    LIBRARY ieee ;

    USE ieee.std_logic_1164.all ;

    library work;

    use work.comppack.all;

    use work.fpupack.all;

    use work.txt_util.all;

    use work.fixed_pkg.all;

    use work.float_pkg.all;

    use work.math_utility_pkg.all;

    ENTITY mega_divide_tb IS

    END ;

    ARCHITECTURE mega_divide_tb_arch OF mega_divide_tb IS

    SIGNAL datab : std_logic_vector (31 downto 0) ;

    SIGNAL clock : STD_LOGIC ;

    SIGNAL result : std_logic_vector (31 downto 0) ;

    SIGNAL dataa : std_logic_vector (31 downto 0) ;

    signal data_areal, data_breal: real;

    COMPONENT mega_divide

    PORT (

    datab : in std_logic_vector (31 downto 0) ;

    clock : in STD_LOGIC ;

    result : out std_logic_vector (31 downto 0) ;

    dataa : in std_logic_vector (31 downto 0) );

    END COMPONENT ;

    BEGIN

    DUT : mega_divide

    PORT MAP (

    datab => datab ,

    clock => clock ,

    result => result ,

    dataa => dataa ) ;

    clock <= not(clock) after 5 ns;

    verify : process

    begin

    data_areal<=1.0;

    data_breal<= 1.0;

    wait until (clock' event and clock= '1' );

    datab<= to_std_logic_vector(to_float32(to_float(data_breal)));

    dataa<= to_std_logic_vector(to_float32(to_float(data_areal)));

    end process verify;

    END ;