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Altera_Forum
Honored Contributor
13 years agoand here is the test bench i am using
LIBRARY ieee ; USE ieee.std_logic_1164.all ; library work; use work.comppack.all; use work.fpupack.all; use work.txt_util.all; use work.fixed_pkg.all; use work.float_pkg.all; use work.math_utility_pkg.all; ENTITY mega_divide_tb IS END ; ARCHITECTURE mega_divide_tb_arch OF mega_divide_tb IS SIGNAL datab : std_logic_vector (31 downto 0) ; SIGNAL clock : STD_LOGIC ; SIGNAL result : std_logic_vector (31 downto 0) ; SIGNAL dataa : std_logic_vector (31 downto 0) ; signal data_areal, data_breal: real; COMPONENT mega_divide PORT ( datab : in std_logic_vector (31 downto 0) ; clock : in STD_LOGIC ; result : out std_logic_vector (31 downto 0) ; dataa : in std_logic_vector (31 downto 0) ); END COMPONENT ; BEGIN DUT : mega_divide PORT MAP ( datab => datab , clock => clock , result => result , dataa => dataa ) ; clock <= not(clock) after 5 ns; verify : process begin data_areal<=1.0; data_breal<= 1.0; wait until (clock' event and clock= '1' ); datab<= to_std_logic_vector(to_float32(to_float(data_breal))); dataa<= to_std_logic_vector(to_float32(to_float(data_areal))); end process verify; END ;