Honored ContributorI would like to write a piece of VHDL code that has code that depends on the Family type (e.g. Cyclone II or Startix II).
Is there a parameter that defines the Family? So that I can use a construction like if (SOME_PARAMETER = "CycloneII") generate ... ... end generate; Can anybody help me into the wright direction? Thanks.
Honored ContributorSome megafunctions like altpll have a VHDL generic (or Verilog parameter) like "intended_device_family => "Stratix II"". I don't know whether Quartus integrated synthesis makes intended_device_family available to the user's code.
Honored ContributorThe intended_device_family generic with megafunctions indicates to my opinion, that Quartus passes no general information regarding device family, otherwise the said entry could be omitted or at least use this information as default.
Honored ContributorIt is probably possible to use comments structures like intended_family or altera_internal to direct the synthesizer to ignore parts of the code depending on the selected target device, but this would probably result in very non-portable and hard to maintain code (assuming you would be able to get documentation about those from Altera).
You might as well write your code in AHDL which has everything you are asking for... Now, all the assignments (including the device family) are available in the TCL environment of the project. The elegant (and portable) solution for your problem would be to write a small tcl script which generates a list of defines/parameters, which then you add to your project or directly into your code (with an include statement for example). Then it's a matter of using ifdef type of directives to switch between different branches of code accordingly, and have a default branch as well for the portability's sake. You can even make the script to run automatically in Quartus at the beginning of a compilation flow, sort of the same approach Altera is using to generate specific code in their megafunctions.Honored ContributorThank you for remembering the Tcl option. Brad recently showed how this technique can be utilized to set Verilog `defines: http://www.alteraforum.com/forum/showthread.php?t=1996
However, there seems to be no similar option for VHDL designs. This means, to create VHDL conditional defines, CONSTANT values, that can be evaluated in GENERATE statements from a Tcl script, you have to produce a VHDL file, that must be included in the project. Not very smart, but straightforward. It's still a question to me, why the FAMILY global assignment (et al) isn't accessible somehow directly from HDL code.
