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Altera_Forum's avatar
Altera_Forum
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17 years ago

Altera Family dependent code

I would like to write a piece of VHDL code that has code that depends on the Family type (e.g. Cyclone II or Startix II). Is there a parameter that defines the Family? So that I can use a const...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Thank you for remembering the Tcl option. Brad recently showed how this technique can be utilized to set Verilog `defines: http://www.alteraforum.com/forum/showthread.php?t=1996

However, there seems to be no similar option for VHDL designs. This means, to create VHDL conditional defines, CONSTANT values, that can be evaluated in GENERATE statements from a Tcl script, you have to produce a VHDL file, that must be included in the project. Not very smart, but straightforward.

It's still a question to me, why the FAMILY global assignment (et al) isn't accessible somehow directly from HDL code.