Altera Cyclone 2 PLL

Question

I've been trying for a while to work with the Cyclone 2's PLL.

In general I want to produce a signal of 100Mhz output with a 25Mhz clk input.

And see if my radio detects it.

In the photos below I've created a clk divider that produce 25Mhz clk and linked it to the pll block

But I can't see the results in the waveform

You can also see in the photos the Programe I used inside the quartus to create the PLL

Maybe I've been Used it wrong

Please halp with this problem.

altera_forum · Answer

You can't drive the PLL's input clock from the divided clock. Quartus will give you an error allong the lines of "inclk[0] must be driven by a non-inverted input clock pin". So, what you're trying isn't going to work.

You need to drive the PLL directly from your clock input pin and adjust the PLL's ratios accordingly.

Cheers,

Alex

altera_forum · Answer

Hi,  I am not sure if the clock divider will mess up the PLL refclk. Generally we will directly connect the PLL refclk to dedicated clock input pin. What is your input clock frequency?

altera_forum · Answer

You mean that I need to sign 50Mhz directly to the input port?  And not with an output of another block?

altera_forum · Answer

Yes. 50MHz straight into the PLL. Quartus won't let you drive the PLL from 'another block' in the way you're trying.  Cheers, Alex

altera_forum · Answer

And what about the pll configuration with the pll's interface  Programe (you can see in the photo)  Can you walk me through?

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Altera Cyclone 2 PLL

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