Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Altera Cyclone 2 PLL

I've been trying for a while to work with the Cyclone 2's PLL. In general I want to produce a signal of 100Mhz output with a 25Mhz clk input. And see if my radio detects it. In the photos b...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

You can't drive the PLL's input clock from the divided clock. Quartus will give you an error allong the lines of "inclk[0] must be driven by a non-inverted input clock pin". So, what you're trying isn't going to work.

You need to drive the PLL directly from your clock input pin and adjust the PLL's ratios accordingly.

Cheers,

Alex