AHDL, VHDL or Verilog?

Is Qsys based on point to point architecture?

alright, thanks

About the emergence of a new HDL language, I'm rather pessimistic. Some fields of the industry are very slow to adapt to new standards. As an example some customers still ask for VHDL'93 and System Verilog, despite it's advantages, isn't as widely used as it should be.

i see SystemVerilog picking up pretty well

i was writing in verilog for couple of years. and came to conclusion that your module may work perfectly in one project, and will not in another. i guess the reason lies in the way verilog itself is engineered. my personal opinion is that no language knows how to treat altera's fpga better than AHDL itself. in verilog you model behavior. and god knows what decisions will synthesis make to satisfy that behavior. since verilog throws you far from gate level , sometimes your behavior is too complex or even errorous to synthesize but you don't sense it anymore.because you lost a gate level vision. you have a demand and want it to be satisfied. that's where things get complicated. verilog tries to swallow everything without questioning. that is why in some projects verilog module works perfectly, and in some other projects it does not. sometimes outside of module, you add a very unimportant multiplexer in addition to the output of your module and it starts to synthesize correctly. remove it - again, module is dead.... sometimes very important registers get synthesized away that leads to catastrophic results.in short nobody knows what will come into synthesis's mind when it tries to put your behavioral model into realization. sometimes it does synthesizes correctly. and sometimes logic drives synthesis so far that it starts to dysfunction. ..change a tiny option in quartus from normal fitting to aggressive one(or vice versa), and your module is again dead... i wonder how could such a colossal barrier was left without notice. people continue working with it as with something unavoidable. it's fine when entire project is yours and you can run after single register but nobody will forgive you at work that you gave them some module that sometimes synthesizes and sometimes not. boss demanded this morning to study AHDL. well... if it came to this.. what choice do i have. what decisions did you made in your life in similar situations people..?

If my company insisted on AHDL, Id find a new job. Its deprecated and altera dont even recommend it.

hmm... iiii... don'tknow! i can simulate AHDL in modelsim same way i do with verilog. or mixed verilog - ahdl project, also simulates perfectly. modelsim needs a netlist of logic gates it does not care about language (i think). and company i work in produces competitive modern hardware on worldwide market. in it, FPGA s (cyclone 4. 115 000 cells) nearly 100% is programmed in AHDL. but i agree that it is an old language and kinda has a prehistoric style synthax :) working with it feels like working with a dinosaur :) and yes it may make me non employable. but trust me if you compare verilog's synthesis stability and AHDL 's synthesis stability, AHDL proved through years that it's synthesis is always correct while verilog may synthesize something away only because the module was copied in a more dense project and compiled. i know you don't believe me but. nobody did before they copied my module. we all had eyes on out foreheads. how is this possible but it is. of course it could be my lack of knowledge and bad coding but i usually run after each register and it's timing. and it worked great on lighter projects where only 20% of fpga was used. as fitter sees that resources are on limits, say close to 90%, the synthesis and fitter simply chews away verilog module parts. again, forgive me if my incompetence makes me say incorrect things... but i am sure many people have observed the same things with verilog. tricky... you are a moderator here so.. your suggestion has a value because you work for altera. so is it true? that altera is planning to withdraw AHDL? that would be a big mistake i think.companies like mine are welded to altera and they can't even look away from it. because of AHDL. xilinx users are also welded to it because of xilinx programming language (i forgot it's name). by withdrawing AHDL altera will simply force people to jump on verilog. which will open their hands -to more freely slide between altera and it's competitors (according to whoever places cheaper prices on better products). you own us guys :D and you are planning to let it go? well i don't know :)))

I dont work for altera, and altera will never remove AHDL support as it would kill too many legacy products (a and check the /db/ folder when you compile - its full of AHDL primitives).