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Altera_Forum
Honored Contributor
Honored ContributorAHDL, VHDL or Verilog?
Hello everyone, I am new with FPGA. Now I would like to learn FPGA but confused with AHDL, VHDL and Verilog. Could anyone describe what are the difference between them? What is your suggest...
Altera_ForumHonored Contributor
Honored ContributorI dont work for altera, and altera will never remove AHDL support as it would kill too many legacy products (a and check the /db/ folder when you compile - its full of AHDL primitives).
Yes, you can simulate AHDL with a netlist - but it is a netlist and hence very very slow. We have simulations that take hours to run with just RTL code - I hate to think how long they would take with a netlist. Hence AHDL is of no use to the majority of the design market for FPGA, and utterly usless for ASIC development. We also use both Altera and Xilinx chips where I work - so portability is a primary concern - so no schematics, no AHDL, and HDL must be as portable as possible - so inference is used most of the time. Most Altera IPs now are done in systemVerilog. With larger designs, Behavioural code is a blessing, not a curse.
