AHDL, VHDL or Verilog?

i was writing in verilog for couple of years. and came to conclusion that your module may work perfectly in one project, and will not in another. i guess the reason lies in the way verilog itself is engineered. my personal opinion is that no language knows how to treat altera's fpga better than AHDL itself. in verilog you model behavior. and god knows what decisions will synthesis make to satisfy that behavior. since verilog throws you far from gate level , sometimes your behavior is too complex or even errorous to synthesize but you don't sense it anymore.because you lost a gate level vision. you have a demand and want it to be satisfied. that's where things get complicated. verilog tries to swallow everything without questioning. that is why in some projects verilog module works perfectly, and in some other projects it does not. sometimes outside of module, you add a very unimportant multiplexer in addition to the output of your module and it starts to synthesize correctly. remove it - again, module is dead.... sometimes very important registers get synthesized away that leads to catastrophic results.in short nobody knows what will come into synthesis's mind when it tries to put your behavioral model into realization. sometimes it does synthesizes correctly. and sometimes logic drives synthesis so far that it starts to dysfunction. ..change a tiny option in quartus from normal fitting to aggressive one(or vice versa), and your module is again dead... i wonder how could such a colossal barrier was left without notice. people continue working with it as with something unavoidable. it's fine when entire project is yours and you can run after single register but nobody will forgive you at work that you gave them some module that sometimes synthesizes and sometimes not. boss demanded this morning to study AHDL. well... if it came to this.. what choice do i have. what decisions did you made in your life in similar situations people..?