AHDL, VHDL or Verilog?

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I dont work for altera, and altera will never remove AHDL support as it would kill too many legacy products (a and check the /db/ folder when you compile - its full of AHDL primitives).

Yes, you can simulate AHDL with a netlist - but it is a netlist and hence very very slow. We have simulations that take hours to run with just RTL code - I hate to think how long they would take with a netlist. Hence AHDL is of no use to the majority of the design market for FPGA, and utterly usless for ASIC development. We also use both Altera and Xilinx chips where I work - so portability is a primary concern - so no schematics, no AHDL, and HDL must be as portable as possible - so inference is used most of the time.

Most Altera IPs now are done in systemVerilog.

With larger designs, Behavioural code is a blessing, not a curse.

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yes, behavioural modelling is a blessing. untill it stabs you in a back. when putting behavior into realization, after compilation you never know what the actual circuit looks like, how it implemented itself. and it changes from compilation to compilation. im not arguing it really revolutionized FPGA and ASIC design but it proved unreliable. and made the circuitory part uncontrollable because even after compilation if you study entire circuit, you recompile it with some additions and you may get totally different circuit because this behavior now may be implemented in some other manner. you must also constantly keep track for the fact that if your model behaves itself one way and in a same time it "may look like" to behave some other way, the synthesis may choose that other way and implement some other circuit. so while writing you must cut all the other paths and constantly clear that out for the synthesis so the compiler has no other chance but to understand exactly what you said.the reason for this lies within the base of HDLs. at any moment i may tell you something that may be understood this way or another. and of course i am not aware of that, i assume that you have got exactly what i said but you could understand it the other way right? and your choice may vary depending on surrounding circumstances; now imagine how hard it is for me to put it in such a way to guarantee that you will always understand this the way i want to :) i am sick and tired of running after the behavioral model but well.. AHDL also uses behavioral models so... i'm just assuming that AHDL is more reliable during synthesis and fitting optimizations that is all.time will tell. now im gonna go study AHDL. i have started it today. i have a strong rope with me just in case. to hung myself if something :D

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yes, behavioural modelling is a blessing. untill it stabs you in a back. when putting behavior into realization, after compilation you never know what the actual circuit looks like, how it implemented itself. and it changes from compilation to compilation.

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I dont know how you write verilog, but when I write VHDL or verilog, I know I will get the same circuit every time. And you can always check the schematic with the RTL and schematic veiwers if there seems to be a problem. Most of the community dont have a problem either. Assuming you follow the coding guidelines properly (which are very standard) then you can usually go straight from good quality RTL simulation to FPGA on the bench without having to resort to schematics.

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im not arguing it really revolutionized FPGA and ASIC design but it proved unreliable. and made the circuitory part uncontrollable because even after compilation if you study entire circuit, you recompile it with some additions and you may get totally different circuit because this behavior now may be implemented in some other manner. you must also constantly keep track for the fact that if your model behaves itself one way and in a same time it "may look like" to behave some other way, the synthesis may choose that other way and implement some other circuit. so while writing you must cut all the other paths and constantly clear that out for the synthesis so the compiler has no other chance but to understand exactly what you said.the reason for this lies within the base of HDLs. at any moment i may tell you something that may be understood this way or another. and of course i am not aware of that, i assume that you have got exactly what i said but you could understand it the other way right? and your choice may vary depending on surrounding circumstances; now imagine how hard it is for me to put it in such a way to guarantee that you will always understand this the way i want to :) i am sick and tired of running after the behavioral model but well.. AHDL also uses behavioral models so... i'm just assuming that AHDL is more reliable during synthesis and fitting optimizations that is all.time will tell. now im gonna go study AHDL. i have started it today. i have a strong rope with me just in case. to hung myself if something :D

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AHDL is very specific - it is almost like writing schematics in code. But this is where the problems come in. Each FF has d,q,set, preset,reset inputs, which doesnt map to newer technologies.

I would HIGHLY recommend you stick with verilog, SV or VHDL if you want to remain employable. If you're having problems with verilog, then you're clearly not writing it properly (other companies dont have the same issues you seem to be having).

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I would HIGHLY recommend you stick with verilog, SV or VHDL if you want to remain employable. If you're having problems with verilog, then you're clearly not writing it properly (other companies dont have the same issues you seem to be having).

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aa... no...? they don't???? well... hmm... that is probably the reason why everyone are so satisfied by verilog. okay, well... since i do not have an academic knowledge (i studied from books) it is most likely that i violate one of the rules....