AHDL -> verilog HDL

i am currently converting an old AHDL design with swedisch comments :eek: into verilog HDL and the Quartus help doesn't help me much

is there anybody who knows AHDL ??

quartus net list viewer and others do not show me how quartus implements the AHDL functionality all primitivs are seperated so not realy a help

the line i am currently trying to understand is this one

adresscounter_b[].ena = bit_puls and (adresscounter_c[]==0 )& p_selnew or we114;

adresscounter_b[].ena

is the enable of a DFF

so in verilog this would start with (forget the always ....)

always @ ( .... )

if ( ... here comes the AHDL enable condition .. )

adresscounter_b[] <= ....

normaly the AHDL & is equal to the verilog & whereas# is |

but how shall i interprete the "and" and the "or" ?

is the above AHDL line

bit_puls and (adresscounter_c[]==0 )& p_selnew or we114

translated into verilog as

bit_puls && ( (adresscounter_c == 0 ) & p_selnew ) || we114

bit_puls is a DFFE

p_selnew SRFFE

we114 a NODE

adresscounter is a DFFE

Any comment greatly welcome.

BTW is there a translater tool ?

Thanks in advance.