Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

AHDL -> verilog HDL

i am currently converting an old AHDL design with swedisch comments :eek: into verilog HDL and the Quartus help doesn't help me much is there anybody who knows AHDL ?? quartus net list viewer...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

because the FPGA the AHDL is runnng at, is and and tooo expensive and the functionality is now included in a much bigger and much cheaper cyclone beside the nios :-)

yes it seems that it is mixed but i wunder if there is some kind of invisible ( ) due to AND instead of &