AHDL -> verilog HDL

My observation was that if the AHDL module was working fine there is no need to translate it into another HDL as Quartus II will nicely deal with it. Maybe just put a nice HDL wrapper around it to include in the NIOS environment?

Tricky is referring to what is the real strength of AHDL: you can build nice state machines where you decide which 'signals' (or 'wires'?) are registered and which not (the ones that have a .clk assignment are), but as Tricky says: beware when translating as you must carefully re-think what was meant by the original author.