Forum Discussion
[Agilex 7F] How to setup my EMIF IPs for the toolkit?
Hi,
I've been trying to reconfigure my existing EMIF IPs to make them reachable from the EMIF toolkit and be able to generate some eye diagrams. The topology I have :
2x EMIF calib IPs
7x EMIF IPs
One calib IP is connected to 3 EMIFs and the other to the 4 remaining. For the calib IPs, I selected "Add EMIF Debug Interface". For the EMIFs I did not do anything since "Note: Calibration Debug Options are set from EMIF Calibration IP which applies to all EMIFs connected to an I/O row".
When opening the system console, I can see the instances in the System Explorer tab, but not in the Toolkit Explorer (I loaded the sof file).
Am I doing something wrong? Note that I DO NOT want to start again from an example design, or let me know if it won't change anything for me in terms of settings, behavior, ...
Also, if there's a way to generate the eye diagram "by hand" from the exported cal_debug port, I am more than interested. If there's any other way to automate the process of generating the eye diagrams, I would also be interested!
Thanks!
8 Replies
- PoletQuentin
New Contributor
Note: I am using Quartus 25.3 to build, 23.4 for the System Console
- sstrell
Super Contributor
Sorry, you have to generate an example design for F-series devices for this to work. It will be based on the settings you've specified for each of the interfaces so it would not be like starting from scratch. The option you enabled for "Add EMIF Debug Interface" should be enabled in both the EMIF and calibration IP. There is a method for multiple EMIF mentioned in the user guide and training.
- PoletQuentin
New Contributor
Hi sstrell and thank you for your reply. Is there really no way around that constraint? Does it mean that I must have two FPGA builds for being able to test my DDR lanes? What does the example designs contains / adds that I can't do by myself in the IP settings or in RTL? Thanks
- PoletQuentin
New Contributor
I just selected the "Add EMIF..." everywhere in my IP settings, and started a new build, without re-doing the config as shown in the slide you shared (as it is super tedious to do...). The compilation's running...
- AdzimZM_Altera
Regular Contributor
Hi PoletQuentin,
You have to generate example design to enable the EMIF Toolkit as mention in User Guide: https://www.intel.com/content/www/us/en/docs/programmable/683216/23-2-2-7-1/enabling-the-emif-toolkit-in-an-existing.html
The System Console will recognize the design to use EMIF Toolkit if it generated example design based.
You can follow the instruction from User Guide to create a design that include 7 EMIF interfaces with 2 CALIP IP. https://www.intel.com/content/www/us/en/docs/programmable/683216/23-2-2-7-1/creating-a-design-example-with-multiple.html
Then you can modify the signal's name in top level design similar to your design, so then, you can copy the pin assignment to new design.
Regards,
Adzim
- PoletQuentin
New Contributor
Hi AdzimZM_Altera,
Thanks for the reply. How can I proceed if I have both EMIF IP and HPS EMIF IP? My 7 IPs are 6 regular IP + 1 HPS one.
Thanks