Forum Discussion
sstrell
Super Contributor
11 days agoSorry, you have to generate an example design for F-series devices for this to work. It will be based on the settings you've specified for each of the interfaces so it would not be like starting from scratch. The option you enabled for "Add EMIF Debug Interface" should be enabled in both the EMIF and calibration IP. There is a method for multiple EMIF mentioned in the user guide and training.
- PoletQuentin8 days ago
New Contributor
Hi sstrell and thank you for your reply. Is there really no way around that constraint? Does it mean that I must have two FPGA builds for being able to test my DDR lanes? What does the example designs contains / adds that I can't do by myself in the IP settings or in RTL? Thanks