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mschiller-nrao's avatar
mschiller-nrao
Icon for New Contributor rankNew Contributor
2 years ago
Solved

Agile X Transciever Design (JESD204C + F-tile) HSSI_PLD_ADAPT_RX_CLUSTER error

How do I correct this error? I do not believe I'm constraining this device as it's in the Auto Tiles. Error(14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing...
Compilation
Hdl
  • mschiller-nrao's avatar
    mschiller-nrao
    2 years ago

    So turns out if I use an external clock for my IOPLL the problem is resolved.

    Dotted line is the configuration in the project above resulting in the error, solid line for userclk (reference to IOPLL) from another FPGA pin works fine:

Harshx's avatar
Harshx
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Hi,


Your design is failing at Design analysis.


Error message:

VHDL error at memory_loader_pkg.vhd(124): file 'f_in' is not open