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mschiller-nrao's avatar
mschiller-nrao
Icon for New Contributor rankNew Contributor
2 years ago
Solved

Agile X Transciever Design (JESD204C + F-tile) HSSI_PLD_ADAPT_RX_CLUSTER error

How do I correct this error? I do not believe I'm constraining this device as it's in the Auto Tiles. Error(14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing...
Compilation
Hdl
  • mschiller-nrao's avatar
    mschiller-nrao
    2 years ago

    So turns out if I use an external clock for my IOPLL the problem is resolved.

    Dotted line is the configuration in the project above resulting in the error, solid line for userclk (reference to IOPLL) from another FPGA pin works fine:

Harshx's avatar
Harshx
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Hi,

Thanks for contacting Intel. I'm assigned to support request.

I'll investigate on this case and get back to you soon once I have any finding. Meanwhile can you please share the following info for my better understanding.


  1. What's the version of Quartus you are using?
  2. Can you share the related files so that I can compile and check for the same error?


Thanks for your patience.


Regards,

Harsh M