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Altera_Forum
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14 years ago

Address decoding logic for read and write in custom ip

Hello everybody,

i want the logic for custom pheripheral which has two slave ports.

first port has these signals 

avs_s0_address : in std_logic_vector(1 downto 0);
avs_s0_chipselect : in std_logic;
avs_s0_write : in std_logic;
avs_s0_writedata: in std_logic_vector(7 downto 0);
avs_s0_byteenable : in std_logic :='1';

i want the address decoding logic for WRITE opetation.

similarly for other port 

avs_s1_address :in std_logic_vector(1 downto 0);
avs_s1_read : in std_logic;
avs_s1_readdata :out std_logic_vector(31 downto 0);
avs_s1_byteenable: in std_logic_vector(3 downto 0) :="0100");

how to make it readdata to READ by avalon interconnect.

kindly give me the solution.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    --- Quote Start --- 

    avs_s1_address :in std_logic_vector(1 downto 0);
avs_s1_read : in std_logic;
avs_s1_readdata :out std_logic_vector(31 downto 0);
avs_s1_byteenable: in std_logic_vector(3 downto 0) :="0100");

    how to make it readdata to READ by avalon interconnect.

    kindly give me the solution.

    --- Quote End ---

    Here is one solution: 

     
avs_s1_readdata <= your_addr_00_reg when (avs_s1_address = "00") else
your_addr_01_reg when (avs_s1_address = "00") else
your_addr_10_reg when (avs_s1_address = "00") else
your_addr_11_reg;

    Where addr_XX_reg is your internal registers that holds whatever the collection of readable registers are for your component.

    Note that readdata does not need to depend on read at all, it is simply a function of the address input.

    Kevin Jennigns
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Dear K_J, 

    signal reg_read_data : std_logic_vector(31 downto 0);
signal rd_en : std_logic;
rd_en<= '1' when avs_s1_read='1' and avs_s1_address="00" else
        '1' when avs_s1_read='1' and avs_s1_address="01" else
        '1' when avs_s1_read='1' and avs_s1_address="10" else
        '1' when avs_s1_read='1' and avs_s1_address="11";
process (clk,reset)
begin
if reset='1' then
reg_read_data<=(others=>'0');
elsif(clk'event and clk='1') then
if rd_en='1' then
avs_s1_readdata<=reg_read_data;
end if;
end if;

    Is this correct solution for READ operation.