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Altera_Forum
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14 years ago

Address decoding logic for read and write in custom ip

Hello everybody, i want the logic for custom pheripheral which has two slave ports. first port has these signals avs_s0_address : in std_logic_vector(1 downto 0); avs_s0_chipsele...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Dear K_J, 

signal reg_read_data : std_logic_vector(31 downto 0);
signal rd_en : std_logic;
rd_en<= '1' when avs_s1_read='1' and avs_s1_address="00" else
        '1' when avs_s1_read='1' and avs_s1_address="01" else
        '1' when avs_s1_read='1' and avs_s1_address="10" else
        '1' when avs_s1_read='1' and avs_s1_address="11";
process (clk,reset)
begin
if reset='1' then
reg_read_data<=(others=>'0');
elsif(clk'event and clk='1') then
if rd_en='1' then
avs_s1_readdata<=reg_read_data;
end if;
end if;

Is this correct solution for READ operation.