Addition of a vector with a integer in vhdl code

Question

There is a vector A(7 down to 0).Now we have to add this vector with an integer(let it be 5).B(7 down to 0) is output.Then how to write the vhdl code.

altera_forum · Answer

it depends what type A and B are. If A is a std_logic_vector you need to first convert it to an unsigned then add the integer. make sure you also include the numeric_std package (and do not add the std_logic_arith package).

if A and B are already unsigned, you can just write:

B <= A + 5;

But we need to see the declaration of A and B to see what code you really need.

altera_forum · Answer

I have written the code as below:

Library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.numeric_std.all;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

entity improc is

port (clk : in std_logic;

ipixel : in std_logic_vector(23 downto 0);

opixel : out std_logic_vector(23 downto 0)

);

end entity improc;

architecture rtl of improc is

begin

process (clk) begin

if rising_edge (clk) then

opixel(23 downto 16) <= std_logic_vector(unsigned( ipixel(23 downto 16)))+ conv_std_logic_vector(unsigned(9,8)));

opixel(15 downto 8) <= std_logic_vector(unsigned( ipixel(15 downto 8)))+ conv_std_logic_vector(unsigned((9,8)));

opixel(7 downto 0) <= std_logic_vector(unsigned( ipixel(7 downto 0)))+ conv_std_logic_vector(unsigned((9,8)));

end if;

end process;

end architecture rtl;

But it gives error.

altera_forum · Answer

The main problem is that you have included std_logic_arith AND numeric_std. They conflict with each other, so you need to remove std_logic_arith (its not standard VHDL. Neither is std_logic_unsigned, but Ill let you keep that)

the answer would then be:

opixel(23 downto 16) <= std_logic_vector( unsigned( ipixel(23 downto 16) ) + 9 );

altera_forum · Answer

Is it necessaryto convert 9 into vector form using conv_std_logic_vector.Beacuse ipixel is 8 bit and 9 is constant.Plearse help...

altera_forum · Answer

No. Like I showed you, you can add an integer to an unsigned number. There is no need to use conv_std_logic_vector because you're adding an integer to an unsigned. (conv_std_logic_vector is NOT standard VHDL).

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Addition of a vector with a integer in vhdl code

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