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Altera_Forum
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13 years ago

Addition of a vector with a integer in vhdl code

There is a vector A(7 down to 0).Now we have to add this vector with an integer(let it be 5).B(7 down to 0) is output.Then how to write the vhdl code.
Altera_Forum's avatar
Altera_Forum
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13 years ago

No. Like I showed you, you can add an integer to an unsigned number. There is no need to use conv_std_logic_vector because you're adding an integer to an unsigned. (conv_std_logic_vector is NOT standard VHDL).