Addition of a vector with a integer in vhdl code

I have written the code as below:

Library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.numeric_std.all;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

entity improc is

port (clk : in std_logic;

ipixel : in std_logic_vector(23 downto 0);

opixel : out std_logic_vector(23 downto 0)

);

end entity improc;

architecture rtl of improc is

begin

process (clk) begin

if rising_edge (clk) then

opixel(23 downto 16) <= std_logic_vector(unsigned( ipixel(23 downto 16)))+ conv_std_logic_vector(unsigned(9,8)));

opixel(15 downto 8) <= std_logic_vector(unsigned( ipixel(15 downto 8)))+ conv_std_logic_vector(unsigned((9,8)));

opixel(7 downto 0) <= std_logic_vector(unsigned( ipixel(7 downto 0)))+ conv_std_logic_vector(unsigned((9,8)));

end if;

end process;

end architecture rtl;

But it gives error.