Occasional ContributorAbout loading constraints
It would be helpful if you could teach me about reading the constraints of the fitter.
There is no particular problem when editing the SDC with Timing Analyzer, but when compiling afterwards, a warning message appears when the fitter reads the SDC.
The steps I followed are as follows.
1) Compile execution. (Since it is a very small design, it is fully compiled.)
2) Start the timing analyzer
3) Execute “Create Timing Netlist”
4) Execute "Read SDC Flie" to display the SDC File list, then open the SDC File to be edited.
5) Editing and saving SDC File.
6) Execute “Read SDC Flie”
7) Execute “Update Timing Netlist”
The message appears as below after the fitter reads the SDC file.
Info (332104): Reading SDC File: 'TFT_RX.sdc'
Warning (332174): Ignored filter at TFT_RX.sdc(15): s_rlo_clk_det[0]|datad could not be matched with a pin
Warning (332049): Ignored set_false_path at TFT_RX.sdc(15): Argument <to> is an empty collection
Info (332050): set_false_path -from [get_ports {RLO_CLK}] -to [get_pins {s_rlo_clk_det[0]|datad}]
When executing 6), there were no warnings or alarms in the timing analyzer messages.
Also, I edit the SDC file using the GUI (Insert Constraint→Set False Path) instead of manually inputting it, and I also search for pins using Name Finder.
Even if 7) was not executed, the result did not change.
The results did not change even if the first compilation was performed up to logic synthesis instead of full compilation.
In addition, there was no warning or alarm when the timing analyzer read the SDC file during full compilation.
It would be helpful if you could teach me the following points in the above situation.
a) Is it correct to understand that the above message means that the fitter ignores the target set_false_path?
b) Is the reason why the above message appears because the pins have not been determined before fitting?
c) If I change -to [get_pins {s_rlo_clk_det[0]|datad}] to -to [get_registers {s_rlo_clk_det[0]}], the above message no longer occurs, but why?
Sorry for the long post, but I would appreciate it if you could explain it to me.
Also, please note that the text may be difficult to understand due to machine translation.
The constraints you used will remove the Unconstrained path being reported out because the -to node (RLO_CLK_node) that is false path is the same.
At the end, designers need to know their design requirement and know where & when to use set_false_path. These constraints tell Timing Analyzer not to analyze specific paths or clock transfers. Once a path has been cut by either of these commands, there is no way to un-cut it, i.e. these constraints have the highest priority.
Regards,
Richard Tan
