Forum Discussion
Occasional ContributorAbout loading constraints
The constraints you used will remove the Unconstrained path being reported out because the -to node (RLO_CLK_node) that is false path is the same.
At the end, designers need to know their design requirement and know where & when to use set_false_path. These constraints tell Timing Analyzer not to analyze specific paths or clock transfers. Once a path has been cut by either of these commands, there is no way to un-cut it, i.e. these constraints have the highest priority.
Regards,
Richard Tan
Super Contributora) Yes.
b) No. It means that your target is not valid. Are you using the Name Finder to search for this pin? Also, why is a clock input getting connected to a register data input (assuming RLO_CLK is a clock)?
c) datad is probably not the correct name for the data input pin of that register. Use the Name Finder to find the correct target for a constraint.
Yamada1Thank you for answering.
Sorry for not explaining enough.
The reason why RLO_CLK is connected to the data input is to detect the rise of RLO_CLK, and the result of checking the input part with Technology Map Viewer (Post-Fitting) is shown in the figure below.
Also, I use Name Finder to search for pins.
"s_rlo_clk_det[0]|datad" can be found in Name Finder as shown below.
In other words, even though you are using the pin name found in Name Finder, the fitter determines that it is not the correct input pin name when reading the SDC file.
We apologize for the inconvenience, but it would be helpful if you could teach us.
