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Yamada1's avatar
Yamada1
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
Solved

About loading constraints

It would be helpful if you could teach me about reading the constraints of the fitter. There is no particular problem when editing the SDC with Timing Analyzer, but when compiling afterwards, a warn...
Timing
  • RichardT_altera's avatar
    RichardT_altera
    2 years ago

    The constraints you used will remove the Unconstrained path being reported out because the -to node (RLO_CLK_node) that is false path is the same.

    At the end, designers need to know their design requirement and know where & when to use set_false_path. These constraints tell Timing Analyzer not to analyze specific paths or clock transfers. Once a path has been cut by either of these commands, there is no way to un-cut it, i.e. these constraints have the highest priority.

    Regards,

    Richard Tan

RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
2 years ago

Does the project has multiple sdc file? If so, could you arrange the affected sdc list so that the impacted sdc file will read last. Go to Settings > Timing Analyzer, then select the affected sdc file and click "Down".

My guess is that the tool might potentially read the sdc file first before the pins get to known by the quartus tool. Thus, it could not find the pins.

Just to understand correctly, you saw the warning message appear during compilation. After compilation, you open the Timing Analyzer and run the sdc command in the console, then the sdc constraints work this time.

Do I understand correctly?

If possible, could you share your design (Project > Archive Project) so that I can investigate it further.

Regards,

Richard Tan

Yamada1's avatar
Yamada1
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Thank you for answering.

Sorry for the lack of explanation.

This time, the design is small and does not use IP, so there is only one SDC file.

Therefore, the constraints are not overwritten.

It is speculated that the cause of this problem is that the tool reads the SDC file before recognizing the pins, but does this mean that it can be avoided by creating constraints during execution up to logic synthesis?

I checked, and the same phenomenon occurs even when constraints are created after logic synthesis.

In addition, since we search for pins using Name Finder, we do not believe that we are setting a pin that does not exist.

Regarding the phenomenon,

　・A warning message is displayed when the fitter reads an SDC file.

　・If you open the Timing Analyzer and read the SDC file after compilation, no warning message will be displayed.

If you understand that, you are correct.

For additional information:

　・A warning message is not displayed when the timing analyzer reads the SDC file during timing analysis during compilation.

It becomes.

We apologize for not providing the design, but please bear with us as it includes customer information.