Forum Discussion
Occasional ContributorAbout loading constraints
The constraints you used will remove the Unconstrained path being reported out because the -to node (RLO_CLK_node) that is false path is the same.
At the end, designers need to know their design requirement and know where & when to use set_false_path. These constraints tell Timing Analyzer not to analyze specific paths or clock transfers. Once a path has been cut by either of these commands, there is no way to un-cut it, i.e. these constraints have the highest priority.
Regards,
Richard Tan
Super ContributorHmmm, that will be hard to debug without the design. Could you share a simplified design without customer information?
To replicate errors by creating a simplified design:
1. Once you have identify the critical functionality that triggers the error in your original design, extract only the essential modules or components from your original design and create a simplified hierarchy.
2. Remove any unnecessary modules or subsystems that are not directly related to the error.
3. Ensure that the design connections and interfaces are properly maintained.
4. Compile the simplified design and ensure that the error reoccurs.
Regards,
Richard Tan
Yamada1Thank you for answering.
As per your suggestion, we will send you a design with only the relevant parts cut out.
We have confirmed that this issue occurs when the design is compiled.
Also, on line 17 of the SDC file, there is a part where a falsity path is set for the output port, and although it seems that the setting itself is set, the number of Unconstrained Output Ports does not decrease and the setting is seems to be ignored.
Although the file is compressed, it is not password protected, so please unzip it and use it.
We apologize for the inconvenience and appreciate your understanding.
