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Yamada1's avatar
Yamada1
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
Solved

About GPIO IP

I'm thinking of using the GPIO IP to receive the data output from the A/D converter to the FPGA at double rate.

It would be helpful if you could teach me the following points.

1) On page 3 of the user guide, it says that it can be used for general applications that are not specialized for LVDS, but does this mean that it cannot be used for applications where the input or output is LVDS?

2) There is a description that it can handle differential signals in "Pad Interface Signal" on page 8 of the user guide, but based on the description on page 3, does it support differential signals other than LVDS?

We apologize for the inconvenience and appreciate your understanding.

Hdl
  • FvM's avatar
    FvM
    2 years ago
    Hi,
    for differential IO standards like LVDS, I'd use option 2. Define a single ended port pin for the signal, assign differential IO in pin planner.

5 Replies

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    2 years ago
    Hi,
    LVDS interfaces on Arria 10 and Cyclone 10 GX are typically using Serdes IP which has additional features like soft-CDR and higher speed. If you don't need this features, you can use GPIO IP.
    • Yamada1's avatar
      Yamada1
      Icon for Occasional Contributor rankOccasional Contributor
      2 years ago

      Thank you for answering.

      The interface of the A/D converter I plan to use is 14-bit parallel LVDS, and since CLK is supplied from the A/D converter, functions such as CDR are not required, so it seems possible to use GPIO IP.

      When using LVDS with GPIO IP, it would be helpful if you could explain the following.

      1) When you try to assign a differential signal with Pin Planner, a "signal name (n)" is created, so if you set PAD_IN and PAD_IN_b to differential pair pins in Assignment Editor and set I/O Standard to LVDS. It's also a differential pair on Pin Planner, but is this the correct way to do it?

      2) If you set the PAD input to single-end (Use differential buffer off) using the GPIO IP and assign PAD_IN as a differential signal using the Pin Planner, the compilation will complete successfully. Can this be considered the same as when the PAD input is made differential (Use differential buffe is on)? Or, since the differential buffer is outside the IP, is it recommended to make the PAD input differential in terms of performance?

      Sorry for the long post, but I would appreciate it if you could enlighten me.

      • FvM's avatar
        FvM
        Icon for Super Contributor rankSuper Contributor
        2 years ago
        Hi,
        for differential IO standards like LVDS, I'd use option 2. Define a single ended port pin for the signal, assign differential IO in pin planner.
  • deepag's avatar
    deepag
    Icon for New Contributor rankNew Contributor
    1 year ago

    Hi team,

    We are facing the issue regarding the same, like we able to get the output when i configure the pins to differential HSTL mode, but we are not getting output when the pins is mapped to lvds standard.

    Could you please help us in this regard.