About GPIO IP

Thank you for answering.

The interface of the A/D converter I plan to use is 14-bit parallel LVDS, and since CLK is supplied from the A/D converter, functions such as CDR are not required, so it seems possible to use GPIO IP.

When using LVDS with GPIO IP, it would be helpful if you could explain the following.

1) When you try to assign a differential signal with Pin Planner, a "signal name (n)" is created, so if you set PAD_IN and PAD_IN_b to differential pair pins in Assignment Editor and set I/O Standard to LVDS. It's also a differential pair on Pin Planner, but is this the correct way to do it?

2) If you set the PAD input to single-end (Use differential buffer off) using the GPIO IP and assign PAD_IN as a differential signal using the Pin Planner, the compilation will complete successfully. Can this be considered the same as when the PAD input is made differential (Use differential buffe is on)? Or, since the differential buffer is outside the IP, is it recommended to make the PAD input differential in terms of performance?

Sorry for the long post, but I would appreciate it if you could enlighten me.