Forum Discussion
Yamada1
Occasional Contributor
Occasional ContributorAbout GPIO IP
I'm thinking of using the GPIO IP to receive the data output from the A/D converter to the FPGA at double rate. It would be helpful if you could teach me the following points. 1) On page 3 of the u...
- Hi,
for differential IO standards like LVDS, I'd use option 2. Define a single ended port pin for the signal, assign differential IO in pin planner.
deepag
New Contributor
New ContributorHi team,
We are facing the issue regarding the same, like we able to get the output when i configure the pins to differential HSTL mode, but we are not getting output when the pins is mapped to lvds standard.
Could you please help us in this regard.
