About DPRAM of IP created with Quartus

Hi,

The write enable (wren) signal is High, together with the byte enable (byteena) signal, control the write operations on the RAM blocks. By default, the byteena signal is high (enabled) and only the wren signal controls the writing.

Reference user guide- https://cdrdv2-public.intel.com/667041/ug_ram_rom-683240-667041.pdf

Regards

Tiwari

Hi,

Please let me know if you have any other query on this.

Regards

Tiwari

Hi,

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Regards

Tiwari