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mikami's avatar
mikami
Icon for New Contributor rankNew Contributor
1 year ago

About DPRAM of IP created with Quartus

Quartus IP を使用して DPRAM を作成しましたが、RD/RW イネーブル信号はアクティブ High ですか、それともアクティブ Low ですか。
Hdl
Jeet14's avatar
Jeet14
Icon for Frequent Contributor rankFrequent Contributor
1 year ago

Hi,


The write enable (wren) signal is High, together with the byte enable (byteena) signal, control the write operations on the RAM blocks. By default, the byteena signal is high (enabled) and only the wren signal controls the writing.

Reference user guide- https://cdrdv2-public.intel.com/667041/ug_ram_rom-683240-667041.pdf


Regards

Tiwari