about clock gating

hi all:

I have a design on Cycloneiii. I am now trying to implement clock gating to reduce power.

design itself:

There is a PLL lock the external clk through the pin, and generate a clk signal to all the ff in the design.

The design has lots of entities (about 20) connecting each other. All the entities work in a serial way, which means, after one entity finish its job, it passes the result to another entity.

clock gating unit:

1, using VHDL to define an entity, which has one latch (or ff), an AND gat; two inputs (ena, clkin), one output (clkout). I think most of you are fammiliar with this structure~~~

2, using the ALTCLKCTRL core of Cycloneiii, disabling the clock select function (clkselect), enable the buffer control (ena) to gate the input clock signal.

how to implement:

After the clk out of PLL, before the clk goes into each entity, I plan to add a clock gating unit on the clk path. They are controlled by the some status signals of the entities dynamically.

question:

I have some problems in the gate-level simulation. I don't think the compiler can handler the clock paths with AND gate in them well. How to solve it??

I am not it is the proper way of clock gating. If it is not, then what it should be??

looking forwards for responds~~~~