--- Quote Start ---
Hi,
what kind of problems do you have in your gatelevel simulation ? Any timing violations
in your timing reports ? How many gated clocks do use ? How many registers are driven by the different gated clocks ?
Kind regards
GPK
--- Quote End ---
The gate level simulation error is that I didnot receive the expected number of data. I think it is becasue the local clock signals are not synchronous. So when the two entities communicate, they may miss the message between them.
There are timing violations of holding time.
I have used about 20 clock gating units, each of them drives all the registers of a certain entity (maybe 20~40 ff). And some of the entities are RAM and FIFO.
Best
Honored Contributor
