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Altera_Forum's avatar
Altera_Forum
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16 years ago

a question in quartus

I have some questions I have a matlab code which i want to convert it to VHDL code.

The idea in the matlab is using for loop where i compute some matrices by using some vectors I have already constructed.

for example if I have syst_bit=[1 2 3 4 5 .......], parity1=[1 2 3 4 5......] and parity2=[1 2 3 4 5......] I will use for loop as follows

for i=1:256

gamma(i)=syst_bit(i)+parity1(i);-- this is simplification to the real equation

end;

for i=1:256

alpha(i)=syst_bit(i)*gamma(i);-- this is simplification to the real equation

end;

for i=1:256

beta(i)=syst_bit(i)*gamma(i);-- this is simplification to the real equation

end;

Ofcourse in matlab there will be no problem at all since the new values of gamma, alpha or beta will be updated before moving to the next line since it's a high programming language.

This should be done for constant number of times(maybe 6 times) on VHDL while receiving the new input to construct new frames (both are done at the same time)

so my idea is creating the needed adders, multipliers, comparators ......

and using for loop in VHDL and on each loop I should put the input on the input wires of this blocks for example

for i in 0 to 255

wire1<=syst_bit(i);

wire2<=parity1(i);

gamma(i)<=wire3;

end loop;

is this right or not?

23 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    your code:

    --- Quote Start ---

    for i in 0 to 255

    wire1<=syst_bit(i);

    wire2<=parity1(i);

    gamma(i)<=wire3;

    end loop;

    is this right or not?

    --- Quote End ---

    wouldn't work, wire1,wire2 will be updated by last value only after 255 useless assignments.

    why not create arrays in vhdl just like those of matlab and add/multiply the elements as required?
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    ok I think i missed a part to explain i am sorry

    for this code

    for i in 0 to 255

    wire1<=syst_bit(i);

    wire2<=parity1(i);

    gamma(i)<=wire3;

    end loop;

    wire1 is the first input to the adder while wire2 is the second one while wire3 is the output

    the block is as follows

    ---------

    wire1---| |

    | adder |-----wire3

    wire3---| |

    --------

    and the equation i want to implement is

    gamma(0)=syst_bit(0)+parity1(0)

    gamma(1)=syst_bit(1)+parity1(1),.......for 256 times

    so i am concerned about 2 things

    1)is this operation in this form right and will work as i wish

    2)will this operation cause timming problem because the real operation is not addition only but huge operations of adding,multiplication,comparing,normalizing,.... and should be done for constant number of times and i have a restriction to finish all this operations before 192 clocks are consumed(which is the time of constructing the new frame which i should do the same operation on)

    Thanks in advance for your help
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    It still does not help the adder. input wire1 or wire2 are not assigned except by sys_bit(255) and parity(255), the rest is thrown away by compiler.

    The VHDL loop is fundamentally different from software loops and is source of confusion. In fact it is a loop only at code level. It is unrolled at compile time and since it is in sequential body then only the last assignment takes over. You must write:

    wire1(i) <=...

    wire2(i) <=...

    As to timing, insert registers everywhere(clked processes) and it should be ok.

    in short:

    for i = 1 to 100 loop

    a <= b(i);

    end loop means it is unrolled to 100 assignments during compile time. Then (a)

    is updated by last value i.e. b(100)
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    does this mean that I should create 256 adder to do this operation inorder to have wire1(0) to wire1(255) or what would be the solution?

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Yes. Thats what you said you want to do, add/multiply each element of array

    But you can go lower if you can fast. you may even use one adder to share between them. just queue them up if your adder speed is 256 times the array data
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    thank u so much for your help but can you please explain more and if it is possible give me an example.sorry for any inconvenience.

    one thing I want to add in some part of the program where i should compute a matrix called alpha which is(8 rows * 256 columns and each is std_logic_vector(31 downto 0))

    i declared it as follows

    type metric_quantizer is record

    metric_state0:std_logic_vector(31 downto 0);

    metric_state1:std_logic_vector(31 downto 0);

    metric_state2:std_logic_vector(31 downto 0);

    metric_state3:std_logic_vector(31 downto 0);

    metric_state4:std_logic_vector(31 downto 0);

    metric_state5:std_logic_vector(31 downto 0);

    metric_state6:std_logic_vector(31 downto 0);

    metric_state7:std_logic_vector(31 downto 0);

    end record;

    type metric_group is array(0 to 255) of metric_quantizer;

    signal alpha:metric_group;

    the problem here that to compute alpha(2).metric_state3 I should use alpha(1).metric_state0 and so on so before computing alpha(2) of any metric_state I should have computed alpha(1) for all metric_state so what will be the solution in the new case

    and again thank u so much for your help
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    You certainly answered your problem, you need to compute value1 before computing value2 and so on (chained computations). Your adders/mult (let us call it computation engine) can be shared if faster than your data speed.

    having 256 x 32 bit adders is quite large but possible. You can go for any TDM figure(Time division multiplexing = time sharing of resource). If your computation engine can be faster than data then you can use a TDM of 2 i.e. share every two data on same resource(128 adders needed) and so on, at the extreme a TDM os 256 needs one computation engine. so it all depends on your speed environment.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Your last example is consuming not less than 64k registers or memory cells. In special cases, Quartus would be able to implement it in internal RAM, but most likely it can't. So you need a pretty large FPGA to implement just the registers. Adding some logical or arithmetical equations operating on the data, the construct most likely doesn't fit any affordable device. Just another spotlight on your way of writing FPGA code.

    Generally number crunchers and special arithmetic units can be perfectly implemented in FPGA. They can be assumed to beat any standard processor or DSP in calculation speed. But they must be well-considered. You have to find a suitable combination of parallel and sequential processing and respective data storage. It surely doesn't work by only copying some statements from MathLab or C code.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    true 64k registers for the data only, but it is well possible in a large fpga memory or it can be in external memory

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    i have already tried the idea of TDM but i got this error

    Error: Out of memory in module quartus_map.exe (2141 megabytes used)

    Error: Current module quartus_map ended unexpectedly

    here i created a finite state machine which has 2 states assumning i have created 128 computing engine in state1 i will use first 128 as input and in state2 i will use second 128

    the code will be as follows

    process(clk,rst,state)

    begin

    --here the part where i create my frames which depend on clock

    if(state=state1)then

    for i in 0 to 128 loop

    wire1(i)<=syst(i);

    wire2(i)<=parity(i);

    gamma(i)<=wire3(i);

    end loop;

    state<=state2;

    elsif(state=state1)then

    for i in 0 to 128 loop

    wire1(i)<=syst(i+128);

    wire2(i)<=parity(i+128);

    gamma(i+128)<=wire3(i);

    end loop;

    state<=state1;

    end if;

    end process;

    that's right?and what about the error