a question in quartus

It still does not help the adder. input wire1 or wire2 are not assigned except by sys_bit(255) and parity(255), the rest is thrown away by compiler.

The VHDL loop is fundamentally different from software loops and is source of confusion. In fact it is a loop only at code level. It is unrolled at compile time and since it is in sequential body then only the last assignment takes over. You must write:

wire1(i) <=...

wire2(i) <=...

As to timing, insert registers everywhere(clked processes) and it should be ok.

in short:

for i = 1 to 100 loop

a <= b(i);

end loop means it is unrolled to 100 assignments during compile time. Then (a)

is updated by last value i.e. b(100)