a question in quartus

ok I think i missed a part to explain i am sorry

for this code

for i in 0 to 255

wire1<=syst_bit(i);

wire2<=parity1(i);

gamma(i)<=wire3;

end loop;

wire1 is the first input to the adder while wire2 is the second one while wire3 is the output

the block is as follows

---------

wire1---| |

| adder |-----wire3

wire3---| |

--------

and the equation i want to implement is

gamma(0)=syst_bit(0)+parity1(0)

gamma(1)=syst_bit(1)+parity1(1),.......for 256 times

so i am concerned about 2 things

1)is this operation in this form right and will work as i wish

2)will this operation cause timming problem because the real operation is not addition only but huge operations of adding,multiplication,comparing,normalizing,.... and should be done for constant number of times and i have a restriction to finish all this operations before 192 clocks are consumed(which is the time of constructing the new frame which i should do the same operation on)

Thanks in advance for your help