Altera_Forum
Honored Contributor
14 years agoA question in megacore simulation with Modelsim
I generated a PCI-E IP with megacore PCI-E compiler. Along with the IP, QuartusII offers a testbench for simulation. I tried to simulate the testbench with Modelsim6.0c (a separate version). Here is the problem: the verilog files include a lot of global parameters as "parameter [7:0] RP_PRI_BUS_NUM = 8'h00 ;". The Modelsim seems not to support the global parameters.
I tried to replace the parameters with "`define", but the mount is big. I think QuartusII should support modelsim very well. There must be a trick to solve it easily. Could anybody tell me? Or should I change to the altera version of modelsim? Thanks.