A question in megacore simulation with Modelsim

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Try vlog -sv? Or Compile->Compile Options, Verilog&System Verilog tab, Check the SystemVerilog checkbox.

If that fails, post an example and I can try it in Modelsim-SE.

Cheers,

Dave

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I have solved the problem. It is easy. Just running the "runtb.do" coming with the megacore testbench. Now everything is OK. (For Modelsim SE, it may generate loading error due to the option “-noimmedca”. Just remove that option.)

I guess the reason why it gave syntax errors is because I added all files to the project and compiled them. (Not wise. Some files are just parts of some modules, which should be used by "`included".) Don't take pain to do that. It will make a lot of trouble.

Thanks.