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Altera_Forum's avatar
Altera_Forum
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14 years ago

A question in megacore simulation with Modelsim

I generated a PCI-E IP with megacore PCI-E compiler. Along with the IP, QuartusII offers a testbench for simulation. I tried to simulate the testbench with Modelsim6.0c (a separate version). Here is ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

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I have tried Modelsim ase 6.6d. But the modelsim gave errors: "Global declarations are illegal in Verilog 2001 syntax".

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Try vlog -sv? Or Compile->Compile Options, Verilog&System Verilog tab, Check the SystemVerilog checkbox.

If that fails, post an example and I can try it in Modelsim-SE.

Cheers,

Dave