a pipelining module

I am designing a pipelining module which takes the outputs (I, Q) from the previous IC (block) as it inputs. After 8 posedge of clock, it will output its result (yI, yQ). At each posedge of clk, yI<=yI+yQ; YQ<=YI-YQ; (iteratively) Therefore, somehow, I need to initialize (yI, YQ) = (I, Q) in the very beginning before the iteration. I use a initial block for this initialization. However, I keep getting warning: initial value for variables (yI, yQ) should not be constant. Any ideas on this problem? What should be the correct way to handle the situation? Simplified module as follows:module test(I, Q, clk yI, yQ);

input signed [17:0] I, Q;

output signed [17:0] yI, yQ;

integer L;

initial begin

yI = I;

yQ=Q; L=0;

end

always @(posedge clk) begin

yI <= yI + yQ;

yQ <= yI - yQ;

L <= L + 1;

end

endmodule