Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

a pipelining module

I am designing a pipelining module which takes the outputs (I, Q) from the previous IC (block) as it inputs. After 8 posedge of clock, it will output its result (yI, yQ). At each posedge of clk, yI<=...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Initial block is normally used to initialize the register.

You are trying to initialize output port in the initial blobk, thix does not make sense.

U can change the output port name and use assignment to assign yL and yQ to these output port. Anyway, initial block is only for simulation purpose only. I think u should have a reset, to initialize during reset.