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Altera_Forum's avatar
Altera_Forum
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11 years ago

7 segment display from 4 bit binary

So I understand what this is supposed to be doing in theory. However in practice I can't find any practical examples. Basically I have a circuit with two 4 bit numbers in, with a switch (S) to select between the two, and the selected number is shown on the 7 segment display.

Could someone please tell me what I need to change for the syntax of this to compile?

Or alternatively if there is an easier way, I would happily use that. From all the examples I could find this seemed like the best way. currently when trying to compile this error displays for each line of the case statement

Error (10500): VHDL syntax error at test2.vhd(37) near text "when"; expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a concurrent statement 


ENTITY test2 IS
PORT(
    AI    :IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    BI    :IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    S                :IN BIT;
    S7    :OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END test2;
ARCHITECTURE behavior OF test2 IS
PROCESS (AI, BI)
BEGIN
IF (S=0)
CASE "AI" is
when "0000"=> S7 <="0000001"; --1
when "0001"=> S7 <="1001111"; --2 (etc)
when "0010"=> S7 <="0010010";
when "0011"=> S7 <="0000110";
when "0100"=> S7 <="1001100"; 
when "0101"=> S7 <="0100100";
when "0110"=> S7 <="0100000";
when "0111"=> S7 <="0001111";
when "1000"=> S7 <="0000000";
when "1001"=> S7 <="0000100";
    
when others => S7 <="1001111"; -- e for error
END CASE;
END IF;
IF (S=1)    
CASE "AI" is
when "0000"=> S7 <="0000001";
when "0001"=> S7 <="1001111";
when "0010"=> S7 <="0010010";
when "0011"=> S7 <="0000110";
when "0100"=> S7 <="1001100";
when "0101"=> S7 <="0100100";
when "0110"=> S7 <="0100000";
when "0111"=> S7 <="0001111";
when "1000"=> S7 <="0000000";
when "1001"=> S7 <="0000100";
    
when others => S7 <="1001111"; -- e for error
END CASE;
END IF;
    
END PROCESS;
    
END behavior;

Thank you so much for your time

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    AI should not be in ""

    Theres a couple of other bugs:

    1. 2nd case statement should use BI

    2. You havent put S in the process sensitivity list.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    So having fixed those, I'm still left with the same amount of errors. I know its something silly with syntax. Here it is having fixed those things 

    
ENTITY test2 IS
PORT(
    AI    :IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    BI    :IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    S                :IN BIT;
    S7    :OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END test2;
ARCHITECTURE behavior OF test2 IS
PROCESS (AI, BI, S)
BEGIN
IF (S=0)
CASE AI is
when "0000"=> S7 <="0000001";
when "0001"=> S7 <="1001111";
when "0010"=> S7 <="0010010";
when "0011"=> S7 <="0000110";
when "0100"=> S7 <="1001100"; 
when "0101"=> S7 <="0100100";
when "0110"=> S7 <="0100000";
when "0111"=> S7 <="0001111";
when "1000"=> S7 <="0000000";
when "1001"=> S7 <="0000100";
    
when others => S7 <="1001111"; -- e for error
END CASE;
END IF;
IF (S=1)    
CASE BI is
when "0000"=> S7 <="0000001";
when "0001"=> S7 <="1001111";
when "0010"=> S7 <="0010010";
when "0011"=> S7 <="0000110";
when "0100"=> S7 <="1001100";
when "0101"=> S7 <="0100100";
when "0110"=> S7 <="0100000";
when "0111"=> S7 <="0001111";
when "1000"=> S7 <="0000000";
when "1001"=> S7 <="0000100";
    
when others => S7 <="1001111"; -- e for error
END CASE;
END IF;
    
END PROCESS;
    
END behavior;

    Keeps telling me every line is expecting a (, end, or an identifier.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Still results in 15 errors. Here's the full error paste up 

    
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
	Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
	Info: Processing started: Sun Nov 09 12:46:10 2014
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off test2 -c test2
Error (10500): VHDL syntax error at test2.vhd(10) near text "PROCESS";  expecting "begin", or a declaration statement
Error (10500): VHDL syntax error at test2.vhd(16) near text "=>";  expecting ";"
Error (10500): VHDL syntax error at test2.vhd(33) near text "when";  expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a concurrent statement
Error (10500): VHDL syntax error at test2.vhd(34) near text "when";  expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a concurrent statement
Error (10500): VHDL syntax error at test2.vhd(35) near text "when";  expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a concurrent statement
Error (10500): VHDL syntax error at test2.vhd(36) near text "when";  expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a concurrent statement
Error (10500): VHDL syntax error at test2.vhd(37) near text "when";  expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a concurrent statement
Error (10500): VHDL syntax error at test2.vhd(38) near text "when";  expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a concurrent statement
Error (10500): VHDL syntax error at test2.vhd(39) near text "when";  expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a concurrent statement
Error (10500): VHDL syntax error at test2.vhd(40) near text "when";  expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a concurrent statement
Error (10500): VHDL syntax error at test2.vhd(41) near text "when";  expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a concurrent statement
Error (10500): VHDL syntax error at test2.vhd(43) near text "when";  expecting "end", or "(", or an identifier ("when" is a reserved keyword), or a concurrent statement
Error (10500): VHDL syntax error at test2.vhd(44) near text "CASE";  expecting ";", or an identifier ("case" is a reserved keyword), or "architecture"
Info: Found 0 design units, including 0 entities, in source file test2.vhd
Error: Quartus II Analysis & Synthesis was unsuccessful. 13 errors, 0 warnings
	Error: Peak virtual memory: 231 megabytes
	Error: Processing ended: Sun Nov 09 12:46:13 2014
	Error: Elapsed time: 00:00:03
	Error: Total CPU time (on all processors): 00:00:03
Error: Quartus II Full Compilation was unsuccessful. 15 errors, 0 warnings