7 segment display from 4 bit binary

So having fixed those, I'm still left with the same amount of errors. I know its something silly with syntax. Here it is having fixed those things

ENTITY test2 IS
PORT(
    AI    :IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    BI    :IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    S                :IN BIT;
    S7    :OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END test2;
ARCHITECTURE behavior OF test2 IS
PROCESS (AI, BI, S)
BEGIN
IF (S=0)
CASE AI is
when "0000"=> S7 <="0000001";
when "0001"=> S7 <="1001111";
when "0010"=> S7 <="0010010";
when "0011"=> S7 <="0000110";
when "0100"=> S7 <="1001100"; 
when "0101"=> S7 <="0100100";
when "0110"=> S7 <="0100000";
when "0111"=> S7 <="0001111";
when "1000"=> S7 <="0000000";
when "1001"=> S7 <="0000100";
    
when others => S7 <="1001111"; -- e for error
END CASE;
END IF;
IF (S=1)    
CASE BI is
when "0000"=> S7 <="0000001";
when "0001"=> S7 <="1001111";
when "0010"=> S7 <="0010010";
when "0011"=> S7 <="0000110";
when "0100"=> S7 <="1001100";
when "0101"=> S7 <="0100100";
when "0110"=> S7 <="0100000";
when "0111"=> S7 <="0001111";
when "1000"=> S7 <="0000000";
when "1001"=> S7 <="0000100";
    
when others => S7 <="1001111"; -- e for error
END CASE;
END IF;
    
END PROCESS;
    
END behavior;