*** Routing fails ***, Router estimated peak interconnect usage exceeding 100%

I have already defined all modules to be inside logiclock. I made their sizes to be auto. Trying different combinations, putting the regions inside each other, it still doesn't work. How can I know which part of the RTL (which module) is in the area with peak interconnect usage so I can make the size big and fixed? It gives me "from" to "to" location cells.

Thanks

Alex

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Also have a look here: http://quartushelp.altera.com/13.0/mergedprojects/optimize/lock/flp_view_logiclock_reg.htm

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Which version of Quartus are you using? Note that the Chip Planner can show routing congestion.

Something seems wrong though, as an average of 24% seems normal and should be easy, while 110% peak is really bad. Try to find the area where it's occurring and see if you can understand why. Note that this is really hard to do, and often impossible. There is no simple reason routing utilization is high, i.e. you might have five hierarchies all routing through an area, and none of them are technically wrong but the combination of them all causes the issue. On top of that, how do you even fix it?

Floorplanning can help, but can also hurt. (I recommend very simple floorplanning, i.e. a few large rectangles with stuff thrown in, and then letting the fitter take care of stuff you don't know about.) Also, you know the design and may have an idea why. If you have memory interfaces on the top and bottom, and your logic talks to them like they're one big memory, that stresses the routing as everything has to go across chip. That's just an example.

Finally, try going to Assignments -> Settings -> Fitter -> More Settings and turn the Placement Effort up to 8. If using Q13.0 or Q13.1, create a quartus.ini file in your project directory and add the following line:

vpr_placement_effort_targets_all_edges = on

This will get the placer to spend a lot more time working on the routability of your design. This is the best way to get the fitter to naturally reduce routability. (Before Q13.0 you don't need the .ini, as it was the default behavior)

I am facing similar issue as the thread originator. Basically, I have a VIP system two MA deinterlacer (5 AV-MM masters for each one) and two frame buffers (2 AV-MM masters for each one) on a Cyclone V part. All these masters are set to be 256bit wide since the memory controller AV-MM port is also set to be 256bit wide. Anyways, after connecting all 14 masters to the memory controller, sometimes it will compile okay and sometimes it won't fit the design. Note if I change everything to 128bit wide, then the design consistently compiles. But I need 256bit bus for larger data transfer. The design has 76% ALM utilization and interconnect uses 28% of devices resources.

What should I try to avoid fitter error:

1) Use pipeline bridge to merge the AV-MM masters into single AV-MM master before connecting to DDR3 controller?

2) Set placement effort to higher value as Rysc suggested?

3) Anything else?