Honored Contributor
Honored ContributorI am facing similar issue as the thread originator. Basically, I have a VIP system two MA deinterlacer (5 AV-MM masters for each one) and two frame buffers (2 AV-MM masters for each one) on a Cyclone V part. All these masters are set to be 256bit wide since the memory controller AV-MM port is also set to be 256bit wide. Anyways, after connecting all 14 masters to the memory controller, sometimes it will compile okay and sometimes it won't fit the design. Note if I change everything to 128bit wide, then the design consistently compiles. But I need 256bit bus for larger data transfer. The design has 76% ALM utilization and interconnect uses 28% of devices resources.
What should I try to avoid fitter error: 1) Use pipeline bridge to merge the AV-MM masters into single AV-MM master before connecting to DDR3 controller? 2) Set placement effort to higher value as Rysc suggested? 3) Anything else?
