Honored Contributor
Honored ContributorWhich version of Quartus are you using? Note that the Chip Planner can show routing congestion.
Something seems wrong though, as an average of 24% seems normal and should be easy, while 110% peak is really bad. Try to find the area where it's occurring and see if you can understand why. Note that this is really hard to do, and often impossible. There is no simple reason routing utilization is high, i.e. you might have five hierarchies all routing through an area, and none of them are technically wrong but the combination of them all causes the issue. On top of that, how do you even fix it? Floorplanning can help, but can also hurt. (I recommend very simple floorplanning, i.e. a few large rectangles with stuff thrown in, and then letting the fitter take care of stuff you don't know about.) Also, you know the design and may have an idea why. If you have memory interfaces on the top and bottom, and your logic talks to them like they're one big memory, that stresses the routing as everything has to go across chip. That's just an example. Finally, try going to Assignments -> Settings -> Fitter -> More Settings and turn the Placement Effort up to 8. If using Q13.0 or Q13.1, create a quartus.ini file in your project directory and add the following line: vpr_placement_effort_targets_all_edges = on This will get the placer to spend a lot more time working on the routability of your design. This is the best way to get the fitter to naturally reduce routability. (Before Q13.0 you don't need the .ini, as it was the default behavior)
