Where does the boot loader come from

Ooops

Type in this line. should be --base=0x08000000 not --base=0x09000000

I ran elf2flash --verbose --log=log.txt --input-Project.elf --output-ProjectOut.srec --base=0x08000000 --end=0x09FFFFFF --reset=0x08000000 -flash=U23 --boot=boot_loader_cfi.srec

For starters, I'd take a look at the boot_loader_sources directory:

<nios2_install_dir>/components/altera_nios2/sdk/src/boot_loader_sources

Cheers,

- slacker

OK i've done that and it looks like a fine boot loader moving 8 bits at a time.

But is this the correct one to use? How do I/you/anyone know?

Did that source generated the srec file of the same name?

thanks

george

Yes, those are the sources for the CFI and EPCS based boot loaders. There's even a Makefile, in this directory, which will build these sources, for you, so you can play around with the source easily....

Personally, I would backup the existing sources prior to doing any serious experiementing, however.

- slacker

Hello Slaker

Are you an Altera person saying that this is the correct loader or just typical user like me.

The reason I ask is that this is a tedious, confusing and time consuming step in the process and I really don't want to spend days just to find out it's not the correct approach.

Please, Please don't take offense since none is intended.

It's the pressures of trying to ship a unit.

Thanks

George

I ran the makefile on the source that came with the NIOS2 kit. I'm using 1.0.

The srec file that was produced matches the srec file Altera provided.

So..............Has anyone used that with sucess???

George

George,

Most anyone who's programmed flash (either CFI or EPCS) on one of Altera's dev. kits has used these bootloaders. They are what's used to boot the "factory" designs.

In the case of the EPCS device, the bootloader gets placed into a small onchip memory that's part of the epcs_controller. When booting from a CFI flash, the bootloader gets prepended to whatever application code you'd like to copy from the flash into volatile memory. The code is pretty well commented, as well!

Cheers,

- slacker

P.S.: Yes, I work for Altera.

Well I've confirmed with Altera Technical that that is the correct boot loader program.

I've programmed the epcs device and I've programmed my flash device with the loader and application code(s).

But on porwe up the epcs configures the FPGA but no code is executed. It seems that the SDRAM 0x400 0000 to 0x7FF FFFF (spacing for clarity) in connected to both the NIOS instruction and data masters. But the flaos 0x800 0000 to 0x9FF FFFF is only connected to the NIOS data master. How can I get the NIOS to execute code from the FLASH.

Reset vector is pointing to FLASH.

gm

George,

Are you sure you programmed the application code into the EPCS? Your reset vector is pointed to the epcs_controller, right? You ensure that all of the rest of the linker sections point to volatile memory, as well.

Additionally, you can't run code from the EPCS flash and you probably wouldn't want to anyway. (very slow) The epcs_controller has a small onchip memory which is filled with the epcs-flavored bootloader when the system is generated and compiled.

The only caveat I would add to this is that this particular flow will not work for Stratix II and EPCS devices.

Regards,

- slacker

I've been speaking with Altera Regional support and..............

It looks like the NIOS instruction master can't access the FLASH.

I have a large SDRAM 0x400 0000 to 0x7FF FFFF that is connected to the NIOS instruction and data master buses. This is working properly. And a FLASH 0x800 0000 to 0x9FF FFFF connected to an avalon tristate bus. That tri state bus controller is also connected to both the NIOS instruction and data masters.

I can access the data in flash reading locations as data. I CAN NOT access the data in flash using DMA transfers. The DMA transfers were selected to show up any weekness in the FLASH interface. I also believe that the DMA transfers perform more like trying to fetch instructinos from FLASH; reads after reads with one clock delat between them. THe Logic Analizer shows the data available out of the FLASH to the FPGA. But no Data is transfered into the SDRAM.

I've concluded that the FLASH-Tristate interface is not working properly. But why is the real question.

GM