Honored Contributor
Honored ContributorI've been speaking with Altera Regional support and..............
It looks like the NIOS instruction master can't access the FLASH. I have a large SDRAM 0x400 0000 to 0x7FF FFFF that is connected to the NIOS instruction and data master buses. This is working properly. And a FLASH 0x800 0000 to 0x9FF FFFF connected to an avalon tristate bus. That tri state bus controller is also connected to both the NIOS instruction and data masters. I can access the data in flash reading locations as data. I CAN NOT access the data in flash using DMA transfers. The DMA transfers were selected to show up any weekness in the FLASH interface. I also believe that the DMA transfers perform more like trying to fetch instructinos from FLASH; reads after reads with one clock delat between them. THe Logic Analizer shows the data available out of the FLASH to the FPGA. But no Data is transfered into the SDRAM. I've concluded that the FLASH-Tristate interface is not working properly. But why is the real question. GM
