Variable Precision DSP in Arria V Devices

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I gave you the code to infer them already.

I suggest reading the VHDL coding guidelines for inference.

http://www.altera.co.uk/literature/hb/qts/qts_qii51007.pdf

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hey,

Thanks for info..

I synthesized following code which I found in the above document. It's inferring dsp and 17 luts for adder, 39 registers. Actually it should infer adder also inside dsp.

module unsig_altmult_accum (dataout, dataa, datab, clk, aclr, clken);

input [7:0] dataa, datab;

input clk, aclr, clken;

output reg[16:0] dataout;

reg [7:0] dataa_reg, datab_reg;

reg [15:0] multa_reg;

wire [15:0] multa;

wire [16:0] adder_out;

assign multa = dataa_reg * datab_reg;

assign adder_out = multa_reg + dataout;

always @ (posedge clk or posedge aclr)

begin

if (aclr)

begin

dataa_reg <= 8'b0;

datab_reg <= 8'b0;

multa_reg <= 16'b0;

dataout <= 17'b0;

end

else if (clken)

begin

dataa_reg <= dataa;

datab_reg <= datab;

multa_reg <= multa;

dataout <= adder_out;

end

end

endmodule

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hey,

Thanks for info..

I synthesized following code which I found in the above document. It's inferring dsp and 17 luts for adder, 39 registers. Actually it should infer adder also inside dsp.

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No it wont. Like we said, the DSPs only have pre-multiplier adders. So you need to do any adition before the multiply to even hope that the adder goes in the DSP.

Finally I found solution. If we don't register multiplier output, it infers adder also into dsp.

with the following code.

wire [35:0] mul_out = ((mul_a_in[17:0]) * (mul_b_in[17:0]));

assign adder_out = $signed(add_c_in[35:0] + mul_out);

it can do (36 bit + (18 x 18)).

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but unless you register the adder output, you're going to get poorer fmax.

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hey tricky,

That registering can be done in dsp itself, Even we can register inputs also once inside dsp.

this is the dsp inside arria v.

http://www.alteraforum.com/forum/attachment.php?attachmentid=9723&stc=1

This is the dsp inside arria V series devices.